1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device which makes use of an organic film as an interlayer insulating film for multilayer wirings.
2. Description of the Related Art
When an organic film is used as an interlayer insulating film for a multilayer wiring, the organic film is arranged beneath the bonding pads, so that there has been a problem that cracks are generated in the organic interlayer film at the time of wirebonding, and the bonding pad tends to come off the substrate together with the organic interlayer film. In order to solve these problems, there is disclosed in Japanese Patent Laid Open No. 57-59339 and Japanese Patent Laid Open No. 62-298137 a technique in which the organic interlayer film is removed partially to provide an aperture which exposes an oxide film on a semiconductor substrate, and form a bonding pad directly above the oxide film within the aperture by extending an upper wiring layer into the aperture.
However, the thickness of the organic interlayer insulating film is about 1.0-2.0 .mu.m per layer, so that the step of the aperture becomes high and the wiring connected to the bonding pad tends to be broken at the edge of the step. This tendency becomes more conspicuous as the number of layers of the multilayer wiring is increased. In order to prevent the breaking of the wiring at the step edge, one might consider to give a slope to the sidewalls of the aperture. However, it leads to an increase in the occupying area of the bonding pad which in turn brings about an increase in the chip size.
In order to prevent the breaking of the wiring at the step edge without creating an increase in the occupying area of the bonding pad, it may be thought of providing a layer which will not give rise to cracks or peeling at the time of bonding, for example, a metallic layer with the same material quality as that of the wiring or bonding pad, between the bonding pad and the oxide film on the semiconductor substrate. The applicant of the present invention formed a pattern with line width of 10 .mu.m and line interval of 2 .mu.m in the element region, and a pattern with 100 .mu.m square at the bonding pad region by the use of an aluminum wiring layer with thickness of 1.0 .mu.m, and then formed a polyimide film to have a thickness of 1 .mu.m in the element region. As a result, a polyimide film having a thickness of 2 .mu.m was obtained on the aluminum pattern of the bonding pad region. This is considered due to heaping of the polyimide at the central parts of the squares which is caused by surface tension when their area is large.
As in the above, in the case of organic interlayer films, thicknesses of films formed differ greatly for the wiring part where step parts exist densely and for the chip periphery where bonding pads are formed, their ratio approaching even about 1 to 2, and creating a new problem based on this circumstance. Namely, there is a substantial difference in the thicknesses of the organic interlayer insulating films for the element region where through-holes are to be opened narrowly and densely and for the bonding pad region where the aperture for the bonding pads is to be opened. Consequently, if the aperture is opened so as to be appropriate for the bonding pad having a large thickness, the through-holes in the element region become too large due to overetching. Therefore, simultaneous formation, in a single lithographic process, of the openings for the bonding pads and the through-holes connecting the wirings with each other, becomes extremely difficult.